Systems work that ships.

Unified Power Format (UPF), standardized as IEEE 1801, describes a circuit’s power intent separately from its logic. Supporting it requires software to understand concepts such as voltage domains, supply states, isolation, and level shifting, then preserve those relationships as a design moves through an EDA flow.

I implemented support for new UPF commands and updated existing command behavior. The work included designing data structures that could parse and store the standard’s information without losing the connections later stages needed. I treated the standard, product requirements, implementation, and verification as one system: clarifying expected behavior, extending the internal representation, and exercising the result through unit, integration, and flow testing. That approach helped keep a specification-heavy feature understandable in the codebase and dependable across the broader flow.

Shipped in a product release.

A cell model can express valid latch or flip-flop behavior even when its internal structure contains redundant state elements. That makes a purely structural classification brittle. The product needed to infer behavior from what the model did: drive inputs, observe outputs, and determine whether the resulting state transitions matched a valid latch or D-type flip-flop.

I developed simulation-driven learning logic for those cases. The algorithm coordinated forward and backward simulation at a high level, selected the order needed to validate behavior, and used the learned input/output relationships to classify the model. I extended the flow to cover scan-cell models with redundant latches or flip-flops, then tested the behavior across the surrounding verification flow. The core challenge was separating incidental structure from observable function so the product could recognize models that were behaviorally valid even when their implementation was less direct.

Expanded model support and shipped in a product release.

RTL-to-gate mapping connects elements in a register-transfer-level hardware description to their corresponding gate-level representation. On large designs, the matching work can become expensive in both execution time and memory, so improvements have to account for the full data flow rather than optimize an isolated loop.

I used Google Perf to locate bottlenecks and then researched Rabin-Karp hashing, Aho-Corasick string matching, and caching techniques as possible ways to improve the mapping algorithm. The useful choice depended on workload shape, lookup reuse, and the memory cost of additional indexes, so I evaluated the techniques as engineering tradeoffs instead of applying them mechanically. I combined profiling evidence with algorithm and data-structure changes, validated the surrounding flow, and mentored a new-hire engineer during the work. The result improved the time and memory efficiency of the mapping path while preserving the product behavior the flow relied on.

Shipped in a product release.